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Preliminary
FM20L08
1Mbit Bytewide FRAM Memory Features
1Mbit Ferroelectric Nonvolatile RAM * Organized as 128Kx8 * Unlimited Read/Write Cycles * NoDelayTM Writes * Page Mode Operation to 33MHz * Advanced High-Reliability Ferroelectric Process SRAM Replacement * JEDEC 128Kx8 SRAM pinout * 60 ns Access Time, 150 ns Cycle Time System Supervisor * Low Voltage monitor drives external /LVL signal * Write protects memory for low voltage condition * Software programmable block write protect Superior to Battery-backed SRAM Modules * No battery concerns * Monolithic reliability * True surface mount solution, no rework steps * Superior for moisture, shock, and vibration * Resistant to negative voltage undershoots Low Power Operation * 3.3V +10%, -5% Power Supply * 22 mA Active Current Industry Standard Configurations * Commercial Temperature 0 C to +70 C * 32-pin "green" TSOP (-TGC)
Description
The FM20L08 is a 128K x 8 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or FRAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and unlimited write endurance make FRAM superior to other types of memory. In-system operation of the FM20L08 is very similar to other RAM devices and can be used as a drop-in replacement for standard SRAM. Read and write cycles may be triggered by /CE or simply by changing the address. The FRAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM20L08 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM. The FM20L08 includes a voltage monitor function that monitors the power supply voltage. It asserts an active-low signal that indicates the memory is writeprotected when VDD drops below a critical threshold. The /LVL output signal may also be suitable for resetting a host microcontroller. When the /LVL signal is low, the memory is protected against an inadvertent access and data corruption.
The FM20L08 also features software-controlled write protection. The memory array is divided into 8 uniform blocks, each of which can be individually write protected. Device specifications are guaranteed over the temperature range 0C to +70C. Pin Configuration
A11 A9 A8 A13 WE DNU A15 VDD LVL A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
Ordering Information FM20L08-60-TGC 60 ns access, 32-pin "Green" TSOP
This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.3 June 2005
Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 Page 1 of 14
FM20L08
16K x 8 block
16K x 8 block
Block & Row Decoder
Address Latch
16K x 8 block
16K x 8 block
A(16:0)
...
16K x 8 block
A(16:3)
16K x 8 block
A(2:0) 16K x 8 block 16K x 8 block
...
Column Decoder CE WE OE Control Logic I/O Latch & Bus Driver DQ(7:0)
VDD LVL VDD Monitor Write Protect
Figure 1. Block Diagram
Pin Description Pin Name Type A(16:0) Input
/CE
Input
/WE
Input
/OE DQ(7:0) /LVL
Input I/O Output
DNU VDD VSS
Supply Supply
Pin Description Address inputs: The 17 address lines select one of 131,072 bytes in the FRAM array. The address value is latched on the falling edge of /CE. Addresses A(2:0) are used for page mode read and write operations. Chip Enable inputs: The device is selected and a new memory access begins when /CE is low. The entire address is latched internally on the falling edge of chip enable. Subsequent changes to the A(2:0) address inputs allow page mode operation. Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM20L08 to write the data on the DQ bus to the FRAM array. The falling edge of /WE latches a new column address for fast page mode write cycles. Output Enable: When /OE is low, the FM20L08 drives the data bus when valid data is available. Deasserting /OE high tri-states the DQ pins. Data: 8-bit bi-directional data bus for accessing the FRAM array. Low Voltage Lockout: When the voltage monitor detects that VDD is below VTP, the /LVL will be asserted low. While /LVL is low, the memory array cannot be accessed which prevents a low voltage write from corrupting data. When VDD is within its normal operating limits, the /LVL signal will be pulled high. Do Not Use: This pin should be left unconnected. Supply Voltage: 3.3V Ground
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FM20L08 Functional Truth Table /CE /WE H X H L H L H L L L X
Notes: 1) 2) 3) 4)
A(16:3) X V No Change Change V X No Change X
A(2:0) X V Change V V V V X
Operation Standby/Idle Read Page Mode Read Random Read /CE-Controlled Write /WE-Controlled Write 2 Page Mode Write 3 Starts Precharge
H=Logic High, L=Logic Low, V=Valid Address, X=Don't Care. /WE-controlled write cycle begins as a Read cycle and A(16:3) is latched then. Addresses A(2:0) must remain stable for at least 15 ns during page mode operation. For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
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FM20L08
Overview
The FM20L08 is a bytewide FRAM memory logically organized as 131,072 x 8 and is accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation which provides higher speed access to addresses within a page (row). An access to a different page requires that either /CE transitions low or the upper address A(16:3) changes. drive the data bus regardless of the state of /OE as long as /WE is low. Input data must be valid when /CE is deasserted high. In a /WE-controlled write, the memory cycle begins on the falling edge of /CE. The /WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if /OE is low, however it will hi-Z once /WE is asserted low. The /CE- and /WE-controlled write timing cases are shown on page 11. In the Write Cycle Timing 2 diagram, the data bus is shown as a hi-Z condition while the chip is write-enabled and before the required setup time. Although this is drawn to look like a mid-level voltage, it is recommended that all DQ pins comply with the minimum VIH/VIL operating levels. Write access to the array begins on the falling edge of /WE after the memory cycle is initiated. The write access terminates on the rising edge of /WE or /CE, whichever comes first. A valid write operation requires the user to meet the access time specification prior to deasserting /WE or /CE. Data setup time indicates the interval during which data cannot change prior to the end of the write access (/WE or /CE high). Unlike other truly nonvolatile memory technologies, there is no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM20L08 provides the user fast access to any data within a row element. Each row has eight column locations. An access can start anywhere within a row and other column locations may be accessed without the need to toggle the /CE pin. For page mode reads, once the first data byte is driven onto the bus, the column address inputs A(2:0) may be changed to a new value. A new data byte is then driven to the DQ pins. For page mode writes, the first write pulse defines the first write access. While /CE is low, a subsequent write pulse along with a new column address provides a page mode write access. Precharge Operation The precharge operation is an internal condition in which the state of the memory is prepared for a new access. Precharge is user-initiated by driving the /CE signal high. It must remain high for at least the minimum precharge time tPC.
Memory Operation
Users access 131,072 memory locations with 8 data bits each through a parallel interface. The FRAM array is organized as 8 blocks each having 2048 rows. Each row has 8 column locations, which allows fast access in page mode operation. Once an initial address has been latched by the falling edge of /CE, subsequent column locations may be accessed without the need to toggle /CE. When /CE is deasserted high, a precharge operation begins. Writes occur immediately at the end of the access with no delay. The /WE pin must be toggled for each write operation. Read Operation A read operation begins on the falling edge of /CE. The falling edge of /CE causes the address to be latched and starts a memory read cycle if /WE is high. Data becomes available on the bus after the access time has been satisfied. Once the address has been latched and the access completed, a new access to a random location (different row) may begin while /CE is still low. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM20L08's /CE-initiated access time is faster than the address cycle time. The FM20L08 will drive the data bus only when /OE is asserted low and the memory access time has been satisfied. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive, the data bus will remain hi-Z. Write Operation Writes occur in the FM20L08 in the same time interval as reads. The FM20L08 supports both /CEand /WE-controlled write cycles. In both cases, the address is latched on the falling edge of /CE. In a /CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the device begins the memory cycle as a write. The FM20L08 will not
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FM20L08
Supply Voltage Monitor
An internal voltage monitor circuit continuously checks the VDD supply voltage. When VDD is below the specified threshold VTP, the monitor asserts the /LVL signal to an active-low state. The FM20L08 locks out access to the memory when VDD is low. This prevents the system from accessing memory when VDD is too low and inadvertently corrupting the data. The /LVL signal may be used as a reset signal or simply as a status indicator that the memory is locked out. On power up, the /LVL signal will begin in a low state signifying that VDD is below the VTP threshold. It will remain low as long as VDD is below that level. Once VDD rises above VTP, a hold-off timer will begin creating the delay tPULV. Once this delay has elapsed, the /LVL signal will go high or inactive. At this time the memory can be accessed. The memory is ready for access prior to tPU as shown in the Electrical Specifications section. The /LVL signal will remain high until VDD drops below the threshold.
completed, the next operation must be a write cycle. The data byte contains the write-protect settings. This value will not be written to the memory array, so the write address is ignored. Rather the byte will be held pending the next cycle, which must be a write of the data complement to the protection settings. If the complement is correct, the write protect settings will be updated. If not, the process is aborted and the address sequence starts over. The data value written after the correct six addresses will not be entered into memory. The protection data byte consists of 8-bits, each associated with the write protect state of a sector. Setting a bit to 1 write protects the corresponding sector; a 0 enables writes for that sector. The following table shows the write-protect sectors with the corresponding bit that controls the write-protect setting. Write Protect Sectors - 16K x8 blocks Sector 7 1FFFFh - 1C000h Sector 6 1BFFFh - 18000h Sector 5 17FFFh - 14000h Sector 4 13FFFh - 10000h Sector 3 0FFFFh - 0C000h Sector 2 0BFFFh - 08000h Sector 1 07FFFh - 04000h Sector 0 03FFFh - 00000h The write-protect address sequence follows: 1. 05555h * 2. 1AAAAh 3. 03333h 4. 1CCCCh 5. 100FFh 6. 0FF00h 7. 1AAAAh 8. 1CCCCh 9. 0FF00h 10. 00000h * If /CE is low entering the sequence, then an address of 00000h must precede 05555h. The address sequence provides a very secure way of modifying the protection. The correct address sequence has a 1 in 5 x 1030 chance of occurring accidentally. A flow chart of the entire write protect operation is shown in Figure 2. As mentioned above, write-protect settings are nonvolatile. The factory default is unprotected.
Software Write Protection
The 128Kx8 address space is divided into 8 sectors (blocks) of 16Kx8 each. Each sector can be individually software write-protected and the settings are nonvolatile. A unique address and command sequence invokes the write protection mode. To modify write protection, the system host must issue six read commands and two write commands. The specific sequence of read addresses must be provided in order to access to the write protect mode. Following the read address sequence, the host must write a data byte that specifies the desired protection state of each sector. For confirmation, the system must then write the complement of the protection byte immediately following the protection byte. Any error that occurs including read addresses in the wrong order, issuing a seventh read address, or failing to complement the protection value will leave the write protection unchanged. The write-protect state machine monitors all addresses, taking no action until the write-protect read/write sequence occurs. During the address sequence, each read will occur as a valid operation and data from the corresponding addresses will be driven onto the data bus. Any address that occurs out of sequence will cause the software protection state machine to start over. After the address sequence is
Rev. 1.3 June 2005
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FM20L08
Normal Memory Operation
Any other operation
Write 1AAAA?
n
Write 1CCCC?
n
y
y
Read 05555h?
n
Hold Data Byte
Read 1AAAA
y n Read 1AAAAh? y n Read 03333h? n Data Complement? n y Write 1CCCC?
Drive write protect data out
Read 00000
y y Write 0FF00 Read 1CCCCh? n
y Read 00000 n
Read 100FFh?
y
Enter new write y protect settings
Read 0FF00?
n
y
Sequence Detector
Change Write Protect Settings
Read Write Protect Settings
Figure 2. Write-Protect State Machine For example, the following sequence write-protects addresses from 00000h to 07FFFh and 10000h to 13FFFh (sectors 0, 1 & 4): Read Read Read Read Read Read Write Write Write Read Address 05555h 1AAAAh 03333h 1CCCCh 100FFh 0FF00h 1AAAAh 1CCCCh 0FF00h 00000h Data 13h ECh -
; ; ; ;
bits 0, 1, 4 = 1 complement of 13h Data is don't care return to Normal Operation
Rev. 1.3 June 2005
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FM20L08
Software Write Protect Timing
CE A(16:0) WE
05555
1AAAA
03333
1CCCC
100FF
0FF00
1AAAA
1CCCC
0FF00
00000
OE DQ(7:0)
Data
Data
SRAM Drop-In Replacement
The FM20L08 has been designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require /CE to toggle for each new address. /CE may remain low indefinitely. While /CE is low, the device automatically detects address changes and a new access is begun. This functionality allows /CE to be grounded as you might with an SRAM. It also allows page mode operation at speeds up to 33MHz.
For applications that require the lowest power consumption, the /CE signal should be active only during memory accesses. The FM20L08 draws supply current in the milliamp range while /CE is low, even if addresses and control signals are static. While /CE is high, the device draws no more than the maximum standby current ISB. The FM20L08 is backward compatible with the 256Kbit FM18L08 device. So, operating the FM20L08 with /CE toggling low on every address is perfectly acceptable.
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FM20L08
Electrical Specifications
Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any signal pin with respect to VSS TSTG TLEAD Storage Temperature Lead Temperature (Soldering, 10 seconds) Ratings -1.0V to +5.0V -1.0V to +5.0V and VIN < VDD+1V -55C to +125C 300 C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 C to +70 C, VDD = 3.3V +10%, -5% unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply 3.135 3.3 3.63 V IDD VDD Supply Current 22 mA 1 ISB Standby Current - CMOS 15 2 A VTP VDD trip point to assert (deassert) /LVL 2.80 2.90 2.99 V 3 ILI Input Leakage Current 4 1 A ILO Output Leakage Current 4 1 A VIH Input High Voltage 2.2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.6 V VOH Output High Voltage (IOH = -1.0 mA) 2.4 V VOL Output Low Voltage (IOL = 2.1 mA) 0.4 V 5 Notes 1. VDD = 3.6V, /CE cycling at minimum cycle time. All inputs at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded. 2. VDD = 3.6V, /CE at VDD, All other pins at CMOS levels (0.2V or VDD-0.2V). 3. This is the VDD trip voltage at which /LVL is asserted or deasserted. When VDD rises above VTP, /LVL will be deasserted 4. 5.
after satisfying tPULV. When VDD drops below VTP, /LVL will be asserted after satisfying tPDLV. VIN, VOUT between VDD and VSS. For the /LVL pin, the test condition is IOL = 80 A when VDD is between 3.135V and 1.2V. The state of the /LVL pin is not guaranteed when VDD is below 1.2V.
Rev. 1.3 June 2005
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FM20L08 Read Cycle AC Parameters (TA = 0 C to +70 C, CL = 30 pF, VDD = 3.3V +10%, -5% unless otherwise specified) -60 Symbol Parameter Min Max Units Notes tRC Read Cycle Time 150 ns tCE Chip Enable Access Time 60 ns tAA Address Access Time 150 ns tOH Output Hold Time 50 ns tAAP Page Mode Address Access Time 25 ns tOHP Page Mode Output Hold Time 5 ns tCA Chip Enable Active Time 60 ns tPC Precharge Time 90 ns tAS Address Setup Time (to /CE low) 5 ns tAH Address Hold Time (/CE-controlled) 60 ns tOE Output Enable Access Time 10 ns tHZ Chip Enable to Output High-Z 15 ns 1 tOHZ Output Enable High to Output High-Z 15 ns 1 Write Cycle AC Parameters (TA = 0 C to +70 C, VDD = 3.3V +10%, -5% unless otherwise specified) -60 Symbol Parameter Min Max Units tWC Write Cycle Time 150 ns tCA Chip Enable Active Time 60 ns tCW Chip Enable to Write Enable High 60 ns tPC Precharge Time 90 ns tPWC Page Mode Write Enable Cycle Time 30 ns tWP Write Enable Pulse Width 15 ns tAS Address Setup Time (to /CE low) 5 ns tAH Address Hold Time (/CE-controlled) 60 ns tASP Page Mode Address Setup Time (to /WE low) 5 ns tAHP Page Mode Address Hold Time (to /WE low) 15 ns tWLC Write Enable Low to /CE High 25 ns tWLA Write Enable Low to A(16:3) Change 25 ns tAWH A(16:3) Change to Write Enable High 150 ns tDS Data Input Setup Time 20 ns tDH Data Input Hold Time 0 ns tWZ Write Enable Low to Output High Z 15 ns tWX Write Enable High to Output Driven 5 ns tWS Write Enable to /CE Low Setup Time 0 ns tWH Write Enable to /CE High Hold Time 0 ns
Notes 1 This parameter is characterized but not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs.
Notes
1 1 2 2
Power Cycle Timing (TA = 0 C to +70 C, VDD = 3.3V +10%, -5% unless otherwise specified) Symbol Parameter Min Max tPULV Power Up to /LVL Inactive Time (VTP to /LVL high) 0 50 tPDLV Power Down to /LVL Active Time (VTP to /LVL low) 0 15 tVF VDD Fall Time 100 Notes 1 Slope measured at any point on VDD waveform.
Units s s s/V
Notes
1
Rev. 1.3 June 2005
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FM20L08 Data Retention (VDD = 3.3V +10%, -5%) Parameter Data Retention Capacitance (TA = 25 C , f=1 MHz, VDD = 3.3V) Symbol Parameter CI/O Input/Output Capacitance (DQ) CIN Input Capacitance
Min 10
Units Years
Notes
Max 8 6
Units pF pF
Notes
AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Output Load Capacitance
0 to 3V 3 ns 1.5V 30 pF
Read Cycle Timing 1 (/CE low, /OE low)
tRC
A(16:0)
tAA tOH tOH
DQ(7:0)
Read Cycle Timing 2 (/CE-controlled)
tCA tPC
CE
tAS tAH
A(16:0)
tOE tHZ
OE
tCE tOHZ
DQ(7:0)
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FM20L08 Page Mode Read Cycle Timing
t CA tPC
CE
tAS
A(16:3) A(2:0) OE
tCE
Col 0
tOE t OHP
Col 1
tAAP
Col 2
tHZ t OHZ
DQ(7:0)
Data 0
Data 1
Data 2
Although sequential column addressing is shown, it is not required.
Write Cycle Timing 1 (/WE-Controlled, /OE low)
t CA t PC
CE
t AS
t CW tWLC
A(16:0)
t WP t WX tDH tDS D in t HZ
WE
t WZ
DQ(7:0)
D out
D out
Write Cycle Timing 2 (/CE-Controlled)
t CA tPC
CE
t AS tAH
A(16:0)
t WH tWS t DS t DH
WE
DQ(7:0)
NOTE: See Write Operation section for detailed description (page 4).
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FM20L08 Write Cycle Timing 3 (/CE low)
t WC tAWH
A(16:0)
t WLA
WE
t WZ tDS D in t DH
tWX
DQ(7:0)
D out
D out
D in
Page Mode Write Cycle Timing
tCA t PC
CE
tAS
t CW tWLC
A(16:3)
tAH t AHP t ASP
A(2:0)
Col 0
tWP
Col 1
t PWC
Col 2
WE
OE
t DS
tDH
DQ(7:0)
Data 0
Data 1
Data 2
Although sequential column addressing is shown, it is not required.
Power Cycle Timing
VDD
VTP t VF tPULV
VDD min 2.0V
LVL
t PDLV
Rev. 1.3 June 2005
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FM20L08
Mechanical Drawing
32-pin Shrunk TSOP-I (8.0 x 13.4 mm) All dimensions in millimeters
13.30-13.55 11.70-11.90 1.20 max
1 2 3
0.50 typ
0.17-0.27 typ
7.90-8.10
0.95-1.05 0.05-0.15 13.30-13.55
R 0.08 min R 0.08-0.20
0.50-0.70
0 - 5
TSOP Package Marking Scheme
Legend: XXXXXX= part number, SP= speed/package/temp (-60TGC) YY=year, WW=work week, LLLLLL= lot code Example: FM20L08-60-TGC, "green" TSOP package, Commercial temp, Year 2005, Work Week 24, Lot 40002T2 RAMTRON FM20L08-60TGC A052440002T2
RAMTRON XXXXXXX-SP YYWWLLLLLL
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FM20L08
Revision History
Revision 0.6 Date 1/30/04 Summary Added Vdd fall time spec. Changed Power Cycle Timing diagram. Added tAWH Write Timing spec. Added typ value to VTP in DC Operating table. Changed software write-protect scheme. Changed /LVL to Output-only pin. Modified Block Diagram, Pin Description and DC Operating tables. Modified package drawing title. Changed tWX, tAAP, and tAWH specs. Added tAH to Write Cycle parameters table. Changed input rise/fall time AC test condition. Changed tVF units. Added "green" package. Reduced to one speed grade and changed to -60 speed grade. Supply voltage 3.3V +10%, -5%. Temp range 0 to +85C. Temp range 0 to +70C. Changed AC timing parameters. Changed part number/ordering information. Changed to Preliminary status. Added "green" packaging option. Added marking scheme. Removed -S packaging option. Changed address setup and IDD specs.
0.61
5/20/04
0.7 0.8 1.0 1.1 1.2 1.3
9/3/04 12/20/04 3/25/05 5/23/05 6/3/05 6/13/05
Rev. 1.3 June 2005
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